Phase locked loop (PLL) circuits often have large power requirements relative to other circuit blocks of a given system or chip. In certain implementations, this may be attributed to the use of certain circuit components and high performance requirements. For example, a PLL circuit may include a static reference bias circuit that is constantly on. In addition, the PLL circuit's charge pump may constantly pump and dump current to and from a loop filter to maintain a desired frequency lock. Also, the PLL circuit's oscillator may run at a relatively high frequency to minimize jitter and cover a desired operating range. Such high frequency operation may also cause the PLL circuit to consume large amounts of dynamic current.
Unfortunately, it is often impractical to turn off PLL circuits to reduce power consumption. For example, PLL circuits may exhibit output signal glitches when powered down and powered up. In addition, if a PLL circuit is part of a larger system that is selectively powered down, then the operation of other circuits in the system may affect the operation of the PLL circuit. In this regard, if the PLL circuit has a feedback path that routes through other circuits of the system, then the operation of the PLL circuit may be delayed until all such circuits are successfully powered back up.
As a result, there is a need for an improved approach to adjusting the power consumption of a PLL circuit that improves upon one or more of the approaches discussed above.